The present invention relates to semiconductor memory devices.
The present invention relates in one aspect to semiconductor memory devices, and particularly to error correction technology by replacing defective memory cells by spare memory cells.
The present invention relates in a second aspect to semiconductor devices, and particularly to associative memory which efficiently performs the mask function of the reference data stored in the memory.
The present invention relates in other aspects to semiconductor devices, and particularly to a memory device that is adapted to a memory of a very large capacity.
Semiconductor memories have now been fabricated at ever high densities, and those of the VLSI (very-large-scale integrated circuit) levels have been mass-produced. Chip size, however, increases with the increase in the degree of integration, causing the yield to decrease. Decrease of yield can be compensated by a so-called error correction technology which restores the defects by replacing a defective memory cell by a spare memory cell that has been provided on the chip in advance. This technology is very effective to increase the yield of semiconductor memories as has been discussed, for example, in IEEE, Transaction on Electron Devices, ED-26, June, 1979, pp. 853-860.
According to the above conventional technique, a defective memory cell is replaced by a spare memory cell in a chip. Therefore, the defects cannot be restored when there exist defects in a number greater than the number of spare memory cells provided on the chip. Further, the defects are usually restored using a tester; i.e., the tester must be used for a period of time required for restoration, resulting in an increased cost for testing the devices.
In the conventional associative memory, the mask function of input inquiry data is performed by matching the inquiry data with the whole content of the associative memory based upon the data written in the mask register, and making access to the output data related to a word that satisfies the inquiry condition in a portion that is not masked.
The apparatus of this kind has been discussed, for example, in Japanese Patent Laid-Open No. 220838/1984, IEEE, Journal of Solid-State Circuits, Vol. SC-20, No. 5, October, 1985, pp. 951-596, and Technical Report of the Association of Electronic Communications, SSD 83-78, 1983, pp. 45-52.
It has also been performed to impart a "don't care" state to the associative memory cells and to effect the masking for each cell, as disclosed, for example, in IEEE, Journal of Solid State Circuits, Vol. SC-7, No. 5, October, 1972, pp. 364-369.
According to the above-mentioned prior art, the content in the mask register must be set again and is searched every time the data is set, or a peripheral circuit must be provided for each of the data lines to write don't care value onto the associative memory cells, resulting in the decrease of searching speed or in the increase of peripheral circuits.
So far, the redundancy for correcting error of semiconductor memory devices has been effected with a data line as a unit or a word line as a unit on a chip. The redundancy has also been effected on a full wafer with a memory unit as a unit.
The latter example has been discussed in IEEE, Journal of Solid-State circuits, Vol. SC-15, No. 4, August, 1980, pp. 677-686.
According to the above prior art, limitation is imposed on the amount of spare memory and, hence, limitation is imposed on the number of defective bits that can be restored. Further, the time required for the redundancy occupies a considerable portion of time required for testing the memory, and drives up the cost for testing to a degree that cannot be neglected in producing the memory devices. In addition, those memories that are not accepted in the redundancy or that cannot be corrected, are thrown away.
The associative memory cells have heretofore been made up of flip-flop type cells that are used for the SRAM. The SRAM type cells feature high operation speeds and low power consumption, and can be easily fabricated.
The SRAM type cell is mentioned in the International Solid State Circuits Conference (ISSCC), Digest of Technical Papers, 1985, pp. 42-43. The DRAM type cell is mentioned in the Technical Digest of International Electron Device Meeting (IEDM), December, 1985, pp. 284-287.
Among these conventional associative memory cells, the static cell has defects in (a) that it requires many transistors to constitute a memory cell, resulting in the decrease in the degree of integration, (b) that in detecting the coincidence of data, the tri-state (1, 0, and don't care) can be processed with difficulty (the circuit becomes complex), and (c) that to make the memory cell non-volatile, back-up must be established relying upon the power source.
The dynamic cell features a high degree of integration but it too has defects in (d) that it requires refresh operation during the operation, making the access time variable that must be waited for, (e) that it requires refresh operation even during the standby operation, needing a larger electric power for back-up than that of the static cell, and (f) that it is susceptible to soft error caused by alpha rays, so that the memory loses reliability.
Among the associative processings, there are a relatively large number of fixed processings. Therefore, it has been urged to make even the associative memory non-volatile from the standpoint of improving performance of the associative processing apparatus and improving easiness for use.